Verilog Simulators?

To run Verilog code directly, you need a Verilog simulator.  Several open-source Verilog simulators are available that are compatible with the explicit-style output of VITO:

To the best of our knowledge, only one of these (veriwell) is also compatible with the implicit-style input to VITO.   In other words, a good development environment for implicit-style state machines starts with Verilog source running on veriwell.  When this source is debugged, VITO can then convert it to explicit-style, which can be simulated or synthesized by most tools.