The disable statement is implemented with restrictions. It is limited to jumping out from inside a labeled block (other than an if or a while.) The disable may not be used to interrupt a block that is executing in parallel. We feel that VITO's semantics for disable are reasonable under these circumstances, but the semantics of disable in VITO may be different than that used by a simulator. In particular, disabling a block that contains a non-blocking assignment allows the assignment to proceed with VITO, but may prevent the assignment in simulation. For example, the following:
module ex17(count,reset,sysclk);
output count;
input sysclk,reset;
reg [7:0] count;
wire sysclk,reset;
always
begin
@(posedge sysclk) #1
count<=@(posedge sysclk) 0;
begin:looplab
forever
begin
@(posedge sysclk) #1
count<=@(posedge sysclk) count + 1;
if(count==4)
begin
disable looplab;
end
end
end
end
endmodule
implements a bottom testing loop in VITO that (in our opinion)
correctly increments count
from 0 through 5. On some simulators, count
(in our opinion) incorrectly stays 4
for two cycles because count<=@(posedge sysclk) count + 1;
is disabled at the same time the loop is exited.
Although implementing disable in VITO violates our principle that simulation should agree with synthesis, we are still making it available with this warning.