| VITOBS | VITOC | VITOCPP | VITOCUDA | Orig VITO | ||
| logic type | 2-value | 2-value | 2-value | 2-value | 4-value | |
| reg size | 1,4,8 or 16 | any, but uses 32 | any, but uses 32 | any, but uses 32 | any | |
| # vars/reg declare | 1 | ignored | 1 | 1 | any | |
| # vars/input declare | ignored | ignored | 1 | 1 | any | |
| # vars/output declare | ignored | ignored | 1 | 1 | any | |
| non-port regs? | yes, but dcl in .bs0 | yes, but dcl in C | no, all vars are ports | no, all vars are ports | yes, without restriction | |
| state storage | global bit vars | global arrays | arrays in class | _vito_state & arg | regs | |
| port treatment | global scalars | global arrays | arrays in class | args to kernel | verilog ports | |
| func use? | no | yes | yes | yes | yes | |
| func dcl? | no | no | no | yes, with restrictions | yes | |
| memory/array? | no | no | no | yes, dim must be hex | yes | |
| array subscript | n/a | n/a | n/a | [scalar] on lhs,rhs | [scalar] on lhs | |
| case? | no | no | no | no | only in function | |
| binary ('h) con? | yes | future feature | future feature | yes | yes | |
| octal ('o) con? | no | future feature | future feature | yes | yes | |
| hex ('h) con? | yes | future feature | future feature | yes | yes | |
| bit select | [con] | [con]or[con:con] | [con] or [con:con] | [con] or [con:con] | no restrictions | |
| concat ({})? | no | no | no | yes, with restrictions | yes, but not on lhs | |
| arith/logic ops | +-*/%~&|^ | C/verilog common | C/verilog common | C/verilog common | all verilog | |
| arith/logic restrictions | () for presidence | C/verilog common | C/verilog common | C/verilog common | all verilog | |
| rel ops | < > == != <= >= | C/verilog common | C/verilog common | C/verilog common | all verilog | |
| rel op syntax | (vc op vc) | C/verilog common | C/verilog common | C/verilog common | all verilog | |
| rel op validity | |x-y|<32768 | C unsigned | C unsigned | C unsigned | all verilog | |
| multi always? | yes | yes | yes | yes | yes | |
| multi insts of 1 module? | no | yes | yes | yes | yes | |
| inst of multi modules? | no | no | yes,uses C++ classes | only if independent | yes | |
| non-implicit code? | no | no | no | no | yes | |
| blocking assignment? | no | no | no | no | only in non-implicit code | |
| datapath | mul/add | mul/add | mul/add | mul/add or ?: | ?: | |
| testbench | in .bs0 and .bs1 | in calling C main | in calling C++ main | separate .cu in kernel | separate .v files | |
| $time | not translated | not translated | not translated | _vito_time | $time | |
| system $ tasks | not allowed | not allowed | not allowed | not allowed | only in non-implicit code | |
| # cycles run | loop in main | loop in C main | loop in C++ main | args to kernel | simulator and/or testbench | |