VITO: Verilog Implicit to One-hot

VITO is a preprocessor that converts implicit style behavioral Verilog into other Verilog that describes a one-hot design. To the best of our knowledge, the output of VITO can then be synthesized into hardware using any of several commercially available Verilog synthesis tools.

The implicit style input to VITO may contain multiple @(posedge sysclk) statements, each corresponding to a state in the machine. The implicit style Verilog may also contain arbitrarily nested control statements (such as if and while .) The resulting Verilog output from VITO describes a one-hot controller using continuous assign statements and simple always blocks (with only one @ and one reg.)


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To use VITO:

VITO was originally developed by Mark G. Arnold and James D. Shuler. Comments, suggestions, or bug reports may be sent to the username "bugs" at the address derived from this website name.

ARM, Parallax, BasicStamp, CUDA, Nvidia, Synopsys, Design Compiler and Verilog are trademarks of their respective owners.

Last updated on 14 Jan 2013