Valid Verilog Module for VITO

To be valid for VITO, a Verilog module must be valid according to the rules of Verilog syntax , and adhere to other restrictions described below. First, the module MUST include:

• the identifier sysclk in its portlist
• the identifier reset in its portlist
• one or more implicit always blocks
• @(posedge sysclk) to begin each state
• at least one @(posedge sysclk) in every loop

• any instantiation of built-in gates
• any instantiation of any other module
• any continuous assign statements
• any task
• any initial block
• unimplemented control statements
• blocking assignment ( = ) in implicit style blocks
• statements prohibited by the synthesis tool

• `define
• arbitrary indentation, whitespace, except for endmodule
• only certain legal control statements
• comments meaningful to the synthesis tool
• non-blocking assignment ( <= ) in implicit style blocks
• blocking assignment ( = ) in non-implicit style blocks
• functions

  There can be no more than 998 behavioral statements. Each identifier must be no more than 30 characters long. There can be no more than 500 <=s. These limits may be changed by recompiling VITO.