Each state in an implicit style block for VITO begins with @(posedge sysclk). This should not be confused with the intra-assignment delay in the non-blocking assignment .
In a simulator, the @(posedge sysclk) causes the block to suspend until the clock edge. This models the behavior of a synchronous state machine which only makes state transitions at the clock edge. The synthesized hardware that can implement this is a synchronous register, such as one constructed from D type flip flops. In order for simulation to agree with the synthesized hardware, it is necessary to put #1 after the @(posedge sysclk) but before any statements within the state. This is necessary because non- blocking assignments take place at the end of the $time of the clock edge. In order to evaluate expressions properly, the #1 delays the simulator until it is certain all variables have the correct values that were scheduled to be stored during the previous clock cycle.
VITO ignores any # delay. VITO produces the same result whether or not it is present.
RTL style code (as in Synopsys) omits the #1 and the @(posedge sysclk) in <=. Simulation of RTL style code does not match synthesis. VITO accepts RTL style code, however its simulation does not match synthesis. Defining macros CLK and ENS allows the same code to work in both contexts.