Non-blocking assignment ( `<=` ) in VITO

The only assignment that VITO permits inside implicit style blocks is non-blocking assignment. VITO accepts two forms of non-blocking assignment:

      a <= @(posedge sysclk) b;

and

      a <= b;

The latter form is known as RTL assignment. The @(posedge sysclk) must occur inside the non-blocking assignment in order for simulation to agree with synthesis, provided that there are #1s at the beginning of each state. There can be no more than 500 non-blocking assignments within the module. This limit can be raised by recompiling VITO.

VITO treats non-blocking assignment without @(posedge sysclk) inside as though it were there. For example, the above two <= are treated as though they are identical. The RTL form is accepted by VITO only for Synopsys compatibility. It is recommended that only the @(posedge sysclk) form be used for new designs. A technique that allows the same source code to work in both contexts is to define two macros (`CLK and `ENS) that would empty strings when using Synopsys syntax, but satisfy the above when simulating. The `CLK macro is used inside the non-blocking assignment:

      a <= `CLK b;

The `ENS macro is used at the beginning of each state. In other words, use:

    
      forever
        begin
          @(posedge sysclk)`ENS
             count<= `CLK count + 1;
        end

Instead of:

    
      forever
        begin
          @(posedge sysclk) #1
             count<=@(posedge sysclk) count + 1;
        end

Non-blocking assignment ( <= ) in VITO

Non-blocking assignment ( `<=` ) in VITO