VITO is a preprocessor that converts implicit style behavioral Verilog into other Verilog that describes a one-hot design. To the best of our knowledge, the output of VITO can then be synthesized into hardware using any of several commercially available Verilog synthesis tools. VITOC is a modified version of this tool which produces C code to allow a VITO-compliant Verilog source to be simulated on an embedded processor with a C compiler. Because VITOC and VITO use modified versions of the same file names, they must be installed in separate directories.
The implicit style input to VITO/VITOC may contain multiple @(posedge sysclk) statements, each corresponding to a state in the machine. The implicit style Verilog may also contain arbitrarily nested control statements (such as if and while .) The resulting C output from VITOC describes a one-hot controller of the kind produced by VITO.)
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To use VITOC:
Last updated on 10 Jan 2013