VITO is a preprocessor that converts implicit style behavioral Verilog into other Verilog that describes a one-hot design. VITO FPOHA is a modified version of this tool which produces the configuration bitstream for a Field Programmable One-Hot Array (FPOHA). Because both this version as well as the original VITO use modified versions of the same file names, they must be installed in separate directories.
The implicit style input to VITO may contain multiple @(posedge sysclk) statements, each corresponding to a state in the machine. The implicit style Verilog may also contain arbitrarily nested control statements (such as if and while .)
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Because of the need for extensive documentation beyond what is given here for the other VITO tools, the source code for the FPOHA and its associated version of VITO are not currently available.
Last updated on 10 Jan 2013