Synopsys, who was one of the first vendors of Verilog synthesis tools in the 1990s, allowed many styles of behavioral Verilog to be converted to hardware. Some of the Verilog features (e.g., blocking assignment ) they supported are essentially like a software language, requiring high-level-synthesis dependency-scheduling algorithms ( see our paper analyzing this ) as complex as later tools that convert orginary high-level languages like SystemC. On the other hand, most designers used (and still use) a more limited and cumbersome explicit-style of RTL code in Verilog. Most other vendors of synthesis tool only support explicit-style Verilog (probably because it captures most of the market with much less R&D).
The original Verilog Implicit to One-hot (VITO) tool was developed in late 1996 in response to this need. VITO is a preprocessor that converts easier-to-use implicit-style Verilog into other Verilog statements that can be synthesized by any commercial synthesis tools. VITO allows a designer to express an algorithm with software-like statements, such as while , and have them converted automatically into hardware. The key feature is the one-hot method for state machines . James Shuler wrote the parser and macro processor that is a front-end to the one-hot code-generation routines written by Mark Arnold. Original VITO was written in UNIX-style C, using tools like lexx and yac, although we made some effort to provide MS-DOS executables. VITO was introduced to the Verilog community in 1997 at the International Verilog Conference, where it won the best-paper award.
Versions of this website have existed at various URLs since that time, at first in academic websites (original 1997 VITO website from web archive ). For many years, it was hosted at a website (vito.com) for people who share this common Italian surname, specifically in the subdomain verilog.vito.com. The owners of vito.com eliminated this service, forcing us to create this subdomain of our own, verilogvito.com. (We hope it was not too hard to find us--we just removed the . between verilog and vito).
One motivation in 1996 for developing original VITO was that Mark Arnold was writing a textbook ( Verilog Digital Computer Design ). Many of the code examples in that book use VITO. The code-generation method used at that time (and shown in the book) prohibited the use of memory (arrays) and also of fork and join. These features were added in later versions of VITO, which slightly changed the appearance of the generated Verilog code.
With support for memory, it became possible to use VITO on more realistic designs, such as a RISC microprocessor. In 1999, Arnold together with Freddy Engineer and Mark Winkel (the AWE team) developed the ARM Workalike Experiment (its authors and acronym are both AWE). AWE is a clone of as much of a full-featured ARM architecture as we could do without infringing on ARM's patents. AWE was presented at WESCON in 1999, and several enhanced versions were used in academic experiments ( see papers ) Our initial premise was VITO made the design of AWE much easier than if we used explicit-style Verilog; much later (2007) S. Langhanoja demonstrated AWE synthesized to be both smaller and faster than a similar clone designed with traditional explicit-style Verilog.
One of the larger designs to use VITO is a custom matrix coprocessor for Model Predictive Control (MPC) that Panos Vouzis designed. This processor implements algorithms for complex operations, like matrix multiply and inversion, directly in hardware, a task that would be much more difficult if coded in explicit style.
One academic experiment involved designing state machines to control microrobots designed by Jung Ho Cho. These tiny (200 um) devices are fabricated using Micro Electro-Mechanical Systems (MEMS) on the same chip as digital logic. Using hardware state machines, instead of CPU-based software, to control the robot cuts the size and cost. Here VITO makes designing robotic algorithms in hardware almost as easy as using software.
This microrobot project was the motivation for development of a different kind of tool inspired by original VITO. Fabricating MEMS chips is expensive, and it is hard to pick up and play with something smaller than a grain of salt. To help us gain intuition about these algorithms, we fabricated the Cylindrical Haptic Asynchronous Robotic Logic Interface (CHARLI), an inexpensive 10cm macrorobot (built from DC motors on a tuna can controlled by a Parallax Basic Stamp microcontroller ). Instead of having to code this with the limited dialect of BASIC supported on this chip, we wanted to use the identical Verilog code that would be synthesized onto the actual microrobots. VITOBS was created by modifying the VITO source code, and adding some sed scripts to massage the generated code to match the syntax requirements of the Basic Stamp. If we had it to do all over again, and had the resources to do so, we would have created a framework to support multiple output languages. Alas, VITO was originally conceived as a Verilog-In-Verilog-Out tool; the newer tools have been developed in this more ad-hoc way.
The newer members of the VITO family now include tools to convert VITO-compatible source Verilog into other high-level languages (BasicStamp, C, C++ and CUDA) for cycle-based simulation. The BasicStamp and C versions are useful when one wishes to design embedded-system software using Verilog; the CUDA version offers the potential to accelerate simulation on multi-core GPUs. The subset of Verilog supported by these tools varies (and is related to our ad-hoc scripting methods and sometimes the limitations of the target language, e.g. BasicStamp). We have put the greatest effort on the VITOCUDA package, including some features outside the one-hot focus of the original VITO, because we think the acceleration of Verilog simulation on a GPU may be of interest to a wider audience. With these features, VITOCUDA is able to simulate the AWE, which we consider to be a realistic-sized example.
Finally, a distinct version of VITO has been exteneded to act as its own synthesis tool, targeting a special kind of programmable logic that we have named Field Programmable One-Hot Array (FPOHA). Unlike the more common Field Programmable Gate Array (FPGA) which can be programmed using the original VITO together with a commercial synthesis tool, the FPOHA is specifically optimized for one-hot designs. Comparing similar Verilog designs (one run through original VITO followed by an FPGA synthesis tool versus the other run through FOPHA VITO), the bitstream size (required to configure the device) is much smaller for the FPOHA than for the FPGA. The FPOHA VITO synthesis has been applied to designs for microrobots (by Jung Cho) and interplanetary microprobes (by Ed Chester).
This site is maintained by Mark Gordon Arnold, co-designer of the original VITO, and author of Verilog Digital Computer Design: Algorithms into Hardware, (1999, Prentice Hall PTR). Thanks to all who helped use and improve VITO, including: T. Bailey, E. Chester, J. H. Cho, J. Cowles, J. Cupal, F. Engineer, S. Langhanoja, D. Luksenberg, N. Sample, J. Shuler (original VITO's other co-designer), P. Vouzis and M. Winkel.
ARM, Parallax, BasicStamp, CUDA, Nvidia, Synopsys, Design Compiler, Xilinx, Virtex and Verilog are trademarks of their respective owners.
Updated Jan. 17, 2013.